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Freescale Semiconductor Advance Information
Document Number: MC34713 Rev. 5.0, 12/2008
5.0 A 1.0 MHz Fully Integrated Single Switch-Mode Power Supply
The 34713 is a highly integrated, space efficient, low cost, single synchronous buck switching regulator with integrated N-channel power MOSFETs. It is a high performance point-of-load (PoL) power supply with the ability to track an external reference voltage in different configurations. Its high efficient 5.0 A continuous output current capability combined with its voltage tracking/sequencing ability and tight output regulation, makes it ideal as a single power supply. The 34713 offers the designer the flexibility of many control, supervisory, and protection functions to allow for easy implementation of complex designs. It is housed in a Pb-free, thermally enhanced, and space-efficient 24-Pin Exposed Pad QFN. Features * 50 m integrated N-channel power MOSFETs * Input voltage operating range from 3.0 to 6.0 V * 1% accurate output voltage, ranging from 0.7 to 3.6 V * Voltage tracking capability in different configurations. * Programmable switching frequency range from 200 kHz to 1.0 MHz with a default of 1.0 MHz * Programmable soft start timing * Over-current limit and short-circuit protection * Thermal shutdown * Output over-voltage and under-voltage detection * Active low power good output signal * Active low shutdown input * Pb-free packaging designated by suffix code EP.
34713
SWITCH-MODE POWER SUPPLY
EP SUFFIX 98ARL10577D 24-PIN QFN
ORDERING INFORMATION
Device MC34713EP/R2 Temperature Range (TA) -40 to 85C Package 24 QFN
(3.0 TO 6.0 V) VIN
VMASTER VIN
34713
PVIN BOOT SW INV VOUT
VREFIN PGND VDDI FREQ ILIM GND
COMP VIN VOUT PG SD MICROCONTROLLER DSP, FPGA, ASIC
Figure 1. 34713 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007-8. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
SD
Thermal Monitoring PG M1 System Reset ILIMIT Discharge Oscillator FREQ Prog Frequency Buck Control Logic System Control
Internal Voltage Regulator M2 VDDI
VIN
BOOT
VIN VBOOT
PVIN
FSW Gate ISENSE Driver
M3 SW
ILIM
Prog Soft Start ISENSE VDDI
Current Monitoring
ILIMIT PWM Comparator M4 PGND COMP
VDDI Bandgap Regulator VBG Ramp Generator
VREFIN VBG GND
Reference Selection M5 Discharge VOUT
Figure 2. 34713 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
-
+
-
Error Amplifier
+
INV
PIN CONNECTIONS
PIN CONNECTIONS
BOOT
VDDI
PVIN 20
24 GND FREQ ILIM PG NC SD 1 2 3 4 5 6 7 VREFIN
23
22
21
19 18 17 PVIN SW SW SW PGND PGND
Transparent Top View PIN 25
PVIN 16 15 14 13 12 PGND
VIN 8 NC
VIN 9 COMP
10 INV
11 VOUT
Figure 3. 34713 Pin Connections Table 1. 34713 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 1 2 3 4 5, 8 6 7 9 10 11 12,13,14 15,16,17 18,19,20 21 22,23 24 Pin Name GND FREQ ILIM PG
NC SD
Pin Function Ground Passive Input Output None Input Input Passive Input Output Ground Output Supply Passive Supply Passive
Formal Name Signal Ground Analog signal ground of IC
Definition
Frequency Adjustment Buck converter switching frequency adjustment pin Soft Start Power Good No Connect Shutdown Voltage Tracking Reference Input Compensation Error Amplifier Inverting Input Output Voltage Discharge FET Power Ground Switching Node Power-Circuit Supply Input Bootstrap Logic-Circuit Supply Input Internal Voltage Regulator Soft Start adjustment Active-low (open drain) power-good status reporting pin No internal connections to these pins. Recommend attaching a 0.1 F capacitor from pin 8 to GND. Shutdown mode input control pin Voltage Tracking Reference voltage input Buck converter external compensation network pin Buck converter error amplifier inverting input pin Discharge FET drain connection (connect to buck converter output capacitors) Ground return for buck converter and discharge FET Buck converter power switching node Buck converter main supply voltage input Bootstrap switching node (connect to bootstrap capacitor) Logic circuits supply voltage input Internal Vdd Regulator (connect filter capacitor to this pin) 34713
VREFIN
COMP
INV VOUT PGND SW PVIN BOOT
VIN
VDDI
Analog Integrated Circuit Device Data Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34713 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
Pin Number 25 Pin Name GND Pin Function Ground Formal Name Thermal Pad Definition Thermal pad for heat transfer. Connect the thermal pad to the analog ground and the ground plane for heat sinking.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Input Supply Voltage (VIN) Pin High Side MOSFET Drain Voltage (PVIN) Pin Switching Node (SW) Pin BOOT Pin (Referenced to SW Pin) PG, VOUT,and SD Pins VDDI, FREQ, ILIM, INV, COMP, and VREFIN Pins Continuous Output Current(1) ESD Voltage(2) Human Body Model Machine Model (MM) Charge Device Model THERMAL RATINGS Operating Ambient Temperature(3) Storage Temperature Peak Package Reflow Temperature During Maximum Junction Temperature Power Dissipation (TA = 85C)(6) Notes 1. Continuous output current capability so long as TJ is TJ(MAX). 2. 3. 4. 5. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), the Machine Model (MM) (CZAP = 200 pF, RZAP = 0 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). The limiting factor is junction temperature, taking into account power dissipation, thermal resistance, and heatsinking. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Maximum power dissipation at indicated ambient temperature Reflow(4),(5) TA TSTG TPPRT TJ(MAX) PD -40 to 85 -65 to +150 Note 5 +150 2.9 C C C C W VESD1 VESD2 VESD3 2000 200 750 V VIN PVIN VSW VBOOT - VSW IOUT -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 3.0 +5.0 V V V V V V A Symbol Value Unit
6.
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RESISTANCE(7) Thermal Resistance, Junction to Ambient, Single-layer Board (1s)(8) Thermal Resistance, Junction to Ambient, Four-layer Board (2s2p) Thermal Resistance, Junction to Board
(10) (9)
Symbol
Value
Unit
RJA RJMA RJB
139 43 22
C/W C/W C/W
Notes 7. The PVIN, SW, and PGND pins comprise the main heat conduction paths. 8. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal. 9. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. There are no thermal vias connecting the package to the two planes in the board. 10. Thermal resistance between the device and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic IC INPUT SUPPLY VOLTAGE (VIN) Input Supply Voltage Operating Range Input DC Supply Current(11) Normal Mode: SD = 1, Unloaded Outputs Input DC Supply Current(11) Shutdown Mode, SD = 0 INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI) Internal Supply Voltage Range BUCK CONVERTER (PVIN, SW, PGND, BOOT, INV, COMP, ILIM) High Side MOSFET Drain Voltage Range Output Voltage Adjustment Range(12),(13) Output Voltage Accuracy(12),(14) Line Regulation(12) Normal Operation, VIN = 3.0 to 6.0 V, IOUT = +5.0 A Load Regulation(12) Normal Operation, IOUT = 0.0 to 5.0 A Error Amplifier Common Mode Voltage Range(12),(13) Output Under-voltage Threshold Output Over-voltage Threshold Continuous Output Current Over-current Limit Soft start Adjusting reference Voltage Range Short-circuit Current Limit High Side N-CH Power MOSFET (M3) IOUT = 1.0 A, VBOOT - VSW = 3.3 V Low Side N-CH Power MOSFET (M4) RDS(ON)(12) IOUT = 1.0 A, VIN = 3.3 V Notes 11. 12. 13. 14. RDS(ON)(12) REGLD -1.0 0.0 -8.0 1.5 1.25 10 6.5 8.5 1.0 1.35 -1.5 8.0 5.0 VDDI 50 % V % % A A V A m REGLN -1.0 1.0 % PVIN VOUT 2.5 0.7 -1.0 6.0 3.6 1.0 V V % VDDI 2.35 2.5 2.65 V IINOFF 100 A IIN 25 mA VIN 3.0 6.0 Symbol Min Typ Max Unit
V
VREF
VUVR VOVR IOUT ILIM VILIM ISHORT RDS(ON)HS RDS(ON)LS
10
-
50
m
Section "MODES OF OPERATION", page 13 has a detailed description of the different operating modes of the 34713 Design information only, this parameter is not production tested. The 1% accuracy is only guaranteed for VEFOUT greater then or equal 0.7 V at room temperature. Overall output accuracy is directly affected by the accuracy of the external feedback network, 1% feedback resistors are recommended
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic M2 RDS(ON) VIN = 3.3 V, M2 is on SW Leakage Current (Standby and Shutdown modes) PVIN Pin Leakage Current Shutdown Mode INV Pin Leakage Current Error Amplifier DC Gain
(15)
Symbol RDS(ON)M2 ISW IPVIN IINV AEA UGBWEA SREA OFFSETEA TSDFET TSDHYFET
Min 1.5 -10 -10 -1.0 -3.0 -
Typ 150 3.0 7.0 0 170 25
Max 4.0 10 10 1.0 3.0 -
Unit A A A dB MHz V/s mV C C
Error Amplifier Unit Gain
Bandwidth(15)
(15) (15)
Error Amplifier Slew Rate
Error Amplifier Input Offset Thermal Shutdown
Threshold(15)
(15)
Thermal Shutdown Hysteresis OSCILLATOR (FREQ)
Oscillator Frequency Adjusting Reference Voltage Range TRACKING (VREFIN, VOUT) VREFIN External Reference Voltage Range(15) VOUT Total Discharge Resistance
(15)
VFREQ
0.0
-
VDDI
V
VREFIN RTDR(M5)
0.0 -
50
1.35 -
V
CONTROL AND SUPERVISORY (SD, PG) SD High Level Input Voltage SD Low Level Input Voltage SD Pin Internal Pull-up Resistor(15) VSDHI VSDLO RSDUP VPGLO IPGLKG 2.0 1.0 0.4 2.0 0.4 V V M V
PG Low Level Output Voltage IPG = 3.0 mA PG Pin Leakage Current M1 is off, Pulled up to VIN Notes 15. Design information only, this parameter is not production tested. -1.0 1.0 A
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 3.0 V VIN 6.0 V, - 40C TA 85C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic BUCK CONVERTER (PVIN, SW, PGND, BOOT) Switching Node (SW) Rise Time(16) (PVIN = 3.3 V, IOUT = 5.0 A) Switching Node (SW) Fall Time(16) (PVIN = 3.3 V, IOUT = 5.0 A) Minimum OFF Time Minimum ON Time Soft Start Duration (Normal Mode) ILIM= 1.25 - 1.49 V 1.50 - 1.81 V 1.82 - 2.13 V 2.14 - 2.50 V Over-current Limit Timer Over-current Limit Retry Time-out Period Output Under-voltage/Over-voltage Filter Delay Timer OSCILLATOR (FREQ) Oscillator Default Switching Frequency Oscillator Frequency tolerance is 10% (FREQ = GND) Oscillator Switching Frequency Range CONTROL AND SUPERVISORY (SD, PG) PG Reset Delay Thermal Shutdown Retry Timeout Period(16) 3.2 1.6 0.8 0.4 10 120 25 ms ms s ms tFALL tOFFMIN tONMIN 20 150 0(17) ns ns ns tRISE 14 ns Symbol Min Typ Max Unit
tSS
-
tLIM tTIMEOUT tFILTER
80 5.0
fSW fSW
200
1.0 -
1000
MHz KHz
tPGRESET tTIMEOUT
8.0 80
-
12 120
ms ms
Notes 16. Design information only, this parameter is not production tested. 17. The regulator has the ability to enter into pulse skip mode when the inductor current ripple reaches the threshold for the LS zero detect, which has a typical value of 500 mA.
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Advanced microprocessor-based systems require compact, efficient, and accurate point-of-load (PoL) power supplies. These PoL supply high current and fast transient response capability while maintaining regulation accuracy. Voltage monitoring (power sequencing) and increased operating frequency are also key features for PoL power supplies. PoL power supplies are non-isolated DC to DC converters that are physically located near their load (on the same printed circuit board) and take their input supply from an intermediate bus. Their close proximity to the load allows for higher efficiency, localized protection, and minimum distribution losses. Their compact design and low component-count also reduces overall system cost. The 34713 is a PoL single-output power supply that embodies an integrated solution that's both highly costeffective and reliable. It utilizes a voltage-mode synchronous buck switching converter topology with integrated low RDS(ON) (50 m) N-channel power MOSFETs for highefficiency operation. It provides an output voltage with an accuracy of less than 2.0%, capable of supplying up to 5.0 A of continuous current. Its power sequencing/tracking abilities makes it ideal for systems with multiple related supply rails. It has an adjustable switching frequency, thus permitting greater design flexibility and optimization over a wide range of operating conditions, and can operate at up to 1.0 MHz to significantly reduce the external components size and cost. It also features an over-current limit control, and protects against output over-voltage, under-voltage, and overtemperature conditions. It also protects the system from short-circuit events and incorporates a power-good output signal to alert the host MCU should a fault occur. Operation can be enabled or disabled by controlling the SD pin, which offers power sequencing capabilities. By monolithically integrating the control and supervisory circuitry along with power-FETs, the 34713 offers a complete, compact, cost-effective, and simple solution to satisfy the PoL needs of today's systems.
FUNCTIONAL PIN DESCRIPTION REFERENCE VOLTAGE INPUT (VREFIN)
The 34713 will track the voltage applied at this pin.
ERROR AMPLIFIER INVERTING INPUT (INV)
Buck converter error amplifier inverting input. Connect the output voltage feedback network to this pin.
FREQUENCY ADJUSTMENT INPUT (FREQ)
The buck converter switching frequency can be adjusted by connecting this pin to an external resistor divider between VDDI and GND pins. The default switching frequency (FREQ pin connected to ground, GND) is set at 1.0 MHz.
COMPENSATION INPUT (COMP)
Buck converter external compensation network connects to this pin. Use a type III compensation network.
INPUT SUPPLY VOLTAGE (VIN) SOFT START ADJUSTMENT INPUT (ILIM)
Soft start timing can be adjusted by applying an external voltage between 1.25 V and VDDI on this pin. IC power supply input voltage. Input filtering is required for the device to operate properly.
POWER GROUND (PGND) SIGNAL GROUND (GND)
Analog ground of the IC. Internal analog signals are referenced to this pin voltage. Buck converter and discharge MOSFET power ground. It is the source of the buck converter low side power MOSFET.
SWITCHING NODE (SW) INTERNAL SUPPLY VOLTAGE OUTPUT (VDDI)
This is the output of the internal bias voltage regulator. Connect a 1.0 F, 6.0 V low ESR ceramic filter capacitor between this pin and the GND pin. Filtering any spikes on this output is essential to the internal circuitry stable operation. Buck converter switching node. This pin is connected to the output inductor.
POWER INPUT VOLTAGE (PVIN)
Buck converter power input voltage. This is the drain of the buck converter high side power MOSFET.
OUTPUT VOLTAGE DISCHARGE PATH (VOUT)
Output voltage of the Buck Converter is connected to this pin. it only serves as the output discharge path once the SD signal is asserted.
BOOTSTRAP INPUT (BOOT)
Bootstrap capacitor input pin. Connect a capacitor (as discussed on page 18) between this pin and the SW pin to
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
enhance the gate of the high side Power MOSFET during switching.
POWER GOOD OUTPUT SIGNAL (PG)
This is an active low open drain output that is used to report the status of the device to a host. This output activates after a successful power up sequence and stays active as long as the device is in normal operation and is not experiencing any faults. This output activates after a 10 ms delay and must be pulled up by an external resistor to a supply voltage (e.g., VIN).
SHUTDOWN INPUT (SD)
If this pin is tied to the GND pin, the device will be in Shutdown mode. If left unconnected or tied to the VIN pin, the device will be in Normal mode. The pin has an internal pullup of 1.5 M.
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
MC34713 - Functional Block Diagram
Internal Bias Circuits
System Control and Logic
Oscillator
Protection Functions
Control and Supervisory Functions
Tracking and Sequencing
Buck Converter
Figure 4. 34713 Block Diagram
INTERNAL BIAS CIRCUITS
This block contains all circuits that provide the necessary supply voltages and bias currents for the internal circuitry. It consists of: * Internal voltage supply regulator: This regulator supplies the VDDI voltage that is used to drive the digital/ analog internal circuits. It is equipped with a Power-OnReset (POR) circuit that watches for the right regulation levels. External filtering is needed on the VDDI pin. This block will turn off during the shutdown mode. * Internal bandgap reference voltage: This supplies the reference voltage to some of the internal circuitry. * Bias circuit: This block generates the bias currents necessary to run all of the blocks in the IC.
down commands. It communicates with the buck converter to manage the switching operation and protects it against any faults.
OSCILLATOR
This block generates the clock cycles necessary to run the IC digital blocks. It also generates the buck converter switching frequency. The switching frequency has a default value of 1.0 MHz and can be programmed by connecting a resistor divider to the FREQ pin, between VDDI and GND pins (See Figure 1).
PROTECTION FUNCTIONS
This block contains the following circuits: * Over-current limit and short-circuit detection: This block monitors the output of the buck converter for over current conditions and short-circuit events and alerts the system control for further command. * Thermal limit detection: This block monitors the temperature of the device for overheating events. If the temperature rises above the thermal shutdown
SYSTEM CONTROL AND LOGIC
This block is the brain of the IC where the device processes data and reacts to it. Based on the status of the SD pin, the system control reacts accordingly and orders the device into the right status. It also takes inputs from all of the monitoring/protection circuits and initiates power up or power
34713
Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
threshold, this block will alert the system control for further commands. * Output over-voltage and under-voltage monitoring: This block monitors the buck converter output voltage to ensure it is within regulation boundaries. If not, this block alerts the system control for further commands.
during shutdown mode. Using this block along with controlling the SD pin can offer the user power sequencing capabilities by controlling when to turn the 34713 output on or off.
BUCK CONVERTER
This block provides the main function of the 34713: DC to DC conversion from an un-regulated input voltage to a regulated output voltage used by the loads for reliable operation. The buck converter is a high performance, fixed frequency (externally adjustable), synchronous buck PWM voltage-mode control. It drives integrated 50 m N-channel power MOSFETs saving board space and enhancing efficiency. The switching regulator output voltage is adjustable with an accuracy of less than 2% to meet today's requirements. Its output has the ability to track the voltage applied at the VREFIN pin. The regulator's voltage control loop is compensated using a type III compensation network, with external components to allow for optimizing the loop compensation, for a wide range of operating conditions. A typical bootstrap circuit with an internal PMOS switch is used to provide the voltage necessary to properly enhance the high side MOSFET gate. The 34713 has the ability to supply up to 5.0 A of continuous current, making it suitable for many high current applications.
CONTROL AND SUPERVISORY FUNCTIONS
This block is used to interface with an outside host. It contains the following circuits: * Shutdown control input: An outside host can put the 34713 device into shutdown mode by sending a logic "0" to the SD pin. * Power good output signal PG: The 34713 can communicate to an external host that a fault has occurred by releasing the drive on the PG pin high, allowing the signal/pin to be pulled high by the external pull-up resistor.
TRACKING AND SEQUENCING
This block allows the output of the 34713 to track the voltage applied at the VREFIN pin in different tracking configurations. This will be discussed in further details later in this document. For power down during a shutdown mode, the 34713 uses internal discharge MOSFET (Figure 2) to discharge the output. The discharge MOSFET is only active
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SD = 0 Shutdown VOUT = Discharge VREF = Discharge PG = 1 SD = 1
VIN < 3.0 V Power Off VOUT=OFF VREF=OFF PG = 1 3.0 V<=VIN<=6.0 V
IOUT>=ISHORT VOUT>VOV Over-voltage VOUT=ON VREF=ON PG = 1 Normal VTT = ON VREF=ON PG = 0 TIMEOUT Expired Short-circuit VOUT=OFF VREF=OFF PG = 1
VOUTVOUT>VUV Under-voltage VOUT=ON VREF=ON VOUT= 170C
TJ<=145C TIMEOUT Expired Thermal Shutdown VOUT=OFF VREF=OFF PG = 1
TIMEOUT Expired Over-current VOUT=OFF VREF=ON PG = 1
IOUT1>=ILIM1 For>=10 ms
Figure 5. Operation Modes Diagram
MODES OF OPERATION
The 34713 has two primary modes of operation: Normal Mode In normal mode, all functions and outputs are fully operational. To be in this mode, the VIN needs to be within its operating range, Shutdown input is high, and no faults are present. This mode consumes the most amount of power. Shutdown Mode In this mode, activated by pulling the SD pin low, the chip is in a shutdown state and the output is disabled and discharged. In this mode, the 34713 consumes the least amount of power since almost all of the internal blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34713 checks the status of the SD pin. If the device is in a shutdown mode, no block will power up and the output will not attempt to ramp. Once the SD pin is released to enable the device, the VDDI internal supply voltage and the bias currents are established and the internal VDDI POR signal is also released. The rest of the
internal blocks will be enabled and the buck converter switching frequency and soft start values are determined by reading the FREQ and ILIM pins respectively. A soft start cycle is then initiated to ramp up the output of the buck converter. The buck converter error amplifier uses the voltage on the VREFIN pin as its reference voltage until VREFIN is equal to 0.7 V, then the error amplifier defaults to the internal 0.7 V reference voltage. This method helps achieve multiple tracking configurations as will be explained later in this document. Soft start is used to prevent the output voltage from overshooting during startup. At initial startup, the output capacitor is at zero volts; VOUT = 0 V. Therefore, the voltage across the inductor will be PVIN during the capacitor charge phase which will create a very sharp di/dt ramp. Allowing the inductor current to rise too high can result in a large difference between the charging current and the actual load current that can result in an undesired voltage spike once the capacitor is fully charged. The soft start is active each time the IC goes out of standby or shutdown mode, power is recycled, or after a fault retry. After a successful start-up cycle where the device is enabled, no faults have occurred, and the output voltage has reached its regulation point, the 34713 pulls the power good
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
output signal low after a 10 ms reset delay, to indicate to the host that the device is in normal operation.
PROTECTION AND DIAGNOSTIC FEATURES
The 34713 monitors the application for several fault conditions to protect the load from overstress. The reaction of the IC to these faults ranges from turning off the outputs to just alerting the host that something is wrong. In the following paragraphs, each fault condition is explained: Output Over-voltage An over-voltage condition occurs once the output voltage goes higher than the rising over-voltage threshold (VOVR). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the output will stay active. To avoid erroneous over-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage falls below the falling over-voltage threshold (VOVF), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. Output Under-voltage An under-voltage condition occurs once the output voltage falls below the falling under-voltage threshold (VUVF). In this case, the power good output signal is pulled high, alerting the host that a fault is present, but the output will stay active. To avoid erroneous under-voltage conditions, a 20 s filter is implemented. The buck converter will use its feedback loop to attempt to correct the fault. Once the output voltage rises above the rising under-voltage threshold (VUVR), the fault is cleared and the power good output signal is pulled low, the device is back in normal operation. Output Over-current This block detects over-current in the Power MOSFETs of the buck converter. It is comprised of a sense MOSFET and a comparator. The sense MOSFET acts as a current detecting device by sampling a ratio of the load current. That sample is compared via the comparator with an internal reference to determine if the output is in over-current or not. If the peak current in the output inductor reaches the over current limit (ILIM), the converter will start a cycle-by-cycle operation to limit the current, and a 10 ms over-current limit timer (tLIM) starts. The converter will stay in this mode of operation until one of the following occurs: * The current is reduced back to the normal level before tLIM expires, and in this case normal operation is regained. * tLIM expires without regaining normal operation, at which point the device turns off the output and the power good output signal is pulled high. At the end of a time-out period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. * The device reaches the thermal shutdown limit (TSDFET) and turns off the output. The power good output signal is pulled high. * The output current keeps increasing until it reaches the short circuit current limit (ISHORT). See below for more details. Short-circuit Current Limit This block uses the same current detection mechanism as the over-current limit detection block. If the load current reaches the ISHORT value, the device reacts by shutting down the output immediately. This is necessary to prevent damage in case of a permanent short-circuit. Then, at the end of a timeout period of 100 ms (tTIMEOUT), the device will attempt another soft start cycle. Thermal Shutdown Thermal limit detection block monitors the temperature of the device and protects against excessive heating. If the temperature reaches the thermal shutdown threshold (TSDFET), the converter output switches off and the power good output signal indicates a fault by pulling high. The device will stay in this state until the temperature has decreased by the hysteresis value and then After a timeout period (TTIMEOUT) of 100 ms, the device will retry automatically and the output will go through a soft start cycle. If successful normal operation is regained, the power good output signal is asserted low to indicate that.
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Compensation Network
VOUT
INV C18 0.02 pF R15 15 k C19 1.9 nF R14 300 R2 12.7 k R12 10 k_nopop FREQ C20 0.910 nF R1 20 k R10 10 k R13 10 k_nopop R11 10 k ILIM 3 4 x SD R7 1k VREFIN D1 LED LED VREFIN C13 0.1 F INV COMP C12 0.1 F C11 0.1 F VOUT 5 6 C14 0.1 F 1 2 VIN VDDI BOOT C15 0.1 F SW PVIN 24 VDDI 23 VIN 22 VIN 21 BOOT 20 PVIN 19 PVIN 18 17 16 15 14 13 SW SW PVIN
COMP
SGND FREQ ILIM
PVIN SW SW
MC34713
PG NC VREFIN COMP VOUT SD SW GND GND GND
PG
VMASTER
VMASTER
PGOOD LED
VIN
GND
R8 10 k R9 10 k
7
8
NC
9
10
INV
11
12
VIN Capacitors
VIN C17 10 F C16 0.1 F
I/O Signals
4.7_nopop PVIN VIN GND R16 J2 3 2 1 J3
Jumpers
PVIN VMASTER STBY_nopop LED 1 2 1 SD 2 CON10A 1 3 5 7 9 J1 2 4 6 8 10 VREFIN PG x SD
Optional nopop
VDDI ILIM R5 POT_50 k_nopop FREQ R6 POT_50 k_nopop
GND VMASTER VOUT
3 2 1
Buck Converter
SW D3 PMEG2010EA _nopop L1 1.5 H VOUT R3 4.7_nopop C7 C6 C8 C9 100 F 100 F 100 F 1 nF_nopop VOUT2 VOUT1
PVIN Capacitors
PVIN
C1 0.1 F
C2 1.0 F
C3 C4 C5 100 F 100 F 100 F
Figure 6. Typical Applications
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TYPICAL APPLICATIONS
COMPONENT SELECTION SWITCHING FREQUENCY SELECTION The switching frequency defaults to a value of 1.0 MHz when the FREQ pin is grounded, and 200 kHz when the FREQ pin is connected to VDDI. Intermediate switching frequencies can be obtained by connecting an external resistor divider to the FREQ pin. The table below shows the resulting switching frequency versus FREQ pin voltage. Table 5. Switching Frequency Adjustment
FREQUENCY 200 253 307 360 413 466 520 573 627 680 733 787 840 893 947 1000 VOLTAGE APPLIED TO PIN FREQ 2.341 - 2.500 2.185 - 2.340 2.029 - 2.184
where,
Maximum OFF time percentage
Switching period.
Drain - to - source resistance of FET
1.873 - 2.028 1.717 - 1.872 1.561 - 1.716 1.405 - 1.560 1.249 - 1.404 1.093 - 1.248 0.936 - 1.092 0.781 - 0.936 0.625 - 0.780 0.469 - 0.624 0.313 - 0.468 0.157 - 0.312 0.000 - 0.156
Winding resistance of Inductor
Output current ripple. OUTPUT FILTER CAPACITOR For the output capacitor, the following considerations are more important than the actual capacitance value, the physical size, the ESR and the voltage rating: Transient Response percentage, TR_% (Use a recommended value of 2 to 4% to assure a good transient response.) Maximum Transient Voltage, TR_v_dip = Vo*TR_% Maximum current step,
RFQH RFQL
VDDI FREQ GND
Inductor Current rise time,
where, Figure 7. Resistor Divider for Frequency Adjustment SELECTION OF THE INDUCTOR Inductor calculation is straight forward, being D_max = Maximum ON time percentage. IO = Rated output current. Vin_min = Minimum input voltage at PVIN As a result, it is possible to calculate
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
BOOT
CBOOT
L
In order to find the maximum allowed ESR,
FSW
Gate Driver
SW VOUT
RS CS RF CX CF
CO RO
PWM Comparitor Ramp Generator
INV
RB
Error Amplifier
+ -
COMP
+ -
The effects of the ESR is often neglected by the designers and may present a hidden danger to the ultimate supply stability. Poor quality capacitors have widely disparate ESR value, which can make the closed loop response inconsistent.
VDDI
VREFIN
Reference Selection
Bandgap Regulator
34713
RO V O = V REF ------ + 1 RB
Figure 9. Type III Compensation Network Consider the crossover frequency, FCROSS, of the open loop
Io
gain at one-tenth of the switching frequency, FSW. Then,
Io_step
Current response
10 F CROSS = ---------------------------2 * R O C F 10 C F = -------------------------------------2 * R O F CROSS
dt_I_rise
Worst case assumption
where RO is a user selected resistor. Knowing the LC frequency, it can be obtained the values of RF and CS:
Figure 8. Transient Parameters
TYPE III COMPENSATION NETWORK
Power supplies are desired to offer accurate and tight regulation output voltages. To accomplish this requires a high DC gain. But with high gain comes the possibility of instability. The purpose of adding compensation to the internal error amplifier is to counteract some of the gains and phases contained in the control-to-output transfer function that could jeopardized the stability of the power supply. The Type III compensation network used for 34713 comprises two poles (one integrator and one high frequency pole to cancel the zero generated from the ESR of the output capacitor) and two zeros to cancel the two poles generated from the LC filter as shown in Figure 9.
This gives as a result,
&
Calculate Rs by placing the Pole 1 at the ESR zero frequency:
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TYPICAL APPLICATIONS
stay enhanced. A 0.1 F capacitor is a good value for this bootstrap element.
LAYOUT GUIDELINES
The layout of any switching regulator requires careful consideration. First, there are high di/dt signals present, and the traces carrying these signals need to be kept as short and as wide as possible to minimize the trace inductance, and therefore reduce the voltage spikes they can create. To do this, an understanding of the major current carrying loops is important. See Figure 10. These loops, and their associated components, should be placed in such a way as to minimize the loop size to prevent coupling to other parts of the circuit. Also, the current carrying power traces and their associated return traces should run adjacent to one another, to minimize the amount of noise coupling. If sensitive traces must cross the current carrying traces, they should be made perpendicular to one another to reduce field interaction. Second, small signal components which connect to sensitive nodes need consideration. The critical small signal components are the ones associated with the feedback circuit. The high impedance input of the error amp is especially sensitive to noise, and the feedback and compensation components should be placed as far from the switch node, and as close to the input of the error amplifier as possible. Other critical small signal components include the bypass capacitors for VIN, VREFIN, and VDDI. Locate the bypass capacitors as close to the pin as possible. The use of a multi-layer printed circuit board is recommended. Dedicate one layer, usually the layer under the top layer, as a ground plane. Make all critical component ground connections with vias to this layer. Make sure that the power ground, PGND, is connected directly to the ground plane and not routed through the thermal pad or analog ground. Dedicate another layer as a power plane and split this plane into local areas for common voltage nets. The IC input supply (VIN) should be connected with a dedicated trace to the input supply. This will help prevent noise from the Buck Regulator's power input (PVIN) from injecting switching noise into the IC's analog circuitry. In order to effectively transfer heat from the top layer to the ground plane and other layers of the printed circuit board, thermal vias need to be used in the thermal pad design. It is recommended that 5 to 9 vias be spaced evenly and have a finished diameter of 0.3 mm.
Equating the Pole 2 to 5 times the Crossover Frequency to achieve a faster response and a proper phase margin, 5 * F CROSS = F 1 ---------------------------------------P2 = CF CX 2 * R F -------------------CF + CX
BOOTSTRAP CAPACITOR
The bootstrap capacitor is needed to supply the gate voltage for the high side MOSFET. This N-Channel MOSFET needs a voltage difference between its gate and source to be able to turn on. The high side MOSFET source is the SW node, so it is not ground and it is floating and moving in voltage, so we cannot just apply a voltage directly to the gate of the high side that is referenced to ground, we need a voltage referenced to the SW node. That is why the bootstrap capacitor is needed for. This capacitor charges during the high side off time, since the low side will be on during that time, so the SW node and the bottom of the bootstrap capacitor will be connected to ground and the top of the capacitor will be connected to a voltage source, so the capacitor will charge up to that voltage source (say 5.0 V). Now when the low side MOSFET switches off and the high side MOSFET switches on, the SW nodes rises up to Vin, and the voltage on the boot pin will be Vcap + Vin. So the gate of the high side will have Vcap across it and it will be able to
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
VIN1
VIN2PVIN and 3 Loop Curr ent HS ON Loop Curr ent HS ON
HS SW1 SD
HS
SW SW2 and 3
Loop Current SD ON LS GND2 and 3 PGND BUCK CONVERTER 1 Loop Current LS ON
Buck Converter BUCK CONVERTER 2 and 3 Figure 10. Current Loops
SOFT START SELECTION
Table 6 shows the voltage that should be applied to the terminal ILIM to get the desired configuration of the soft start timing.
Table 6. ILIM Table
Soft Start (ms) 3.2 1.6 0.8 0.4 Voltage Applied to ILIM 1.25 - 1.49 1.50 - 1.81 1.82 - 2.13 2.14 - 2.50
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
EP SUFFIX 24-PIN 98ARL10577D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGING DIMENSIONS
EP SUFFIX 24-PIN 98ARL10577D ISSUE B
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION 1.0 2.0
DATE 2/2006 11/2006
DESCRIPTION OF CHANGES * * * * * * * * * * * * * * * * * * * * * * * * * Pre-release version Implemented Revision History page Initial release Converted format from Market Assessment to Product Preview Major updates to the data, form, and style Major updates to the data, form, and style Changed Feature fom 2% to 1%, relabeled to include soft start Changed 34713 Simplified Application Diagram Made change to 34713 Simplified Internal Block Diagram Removed Machine Model in Maximum Ratings Changed Input DC Supply Current(11) Normal mode and Input DC Supply Current(11) Shutdown mode Changed Output Voltage Accuracy(12),(14) Changed Soft start Adjusting reference Voltage Range and Short-circuit Current Limit Changed High Side N-CH Power MOSFET (M3) RDS(ON)(12) and Low Side N-CH Power MOSFET (M4) RDS(ON)(12) Changed M2 RDS(ON) and PVIN Pin Leakage Current Changed SD Pin Internal Pull-up Resistor(15) Changed Changed Soft Start Duration (Normal Mode) Changed Over-current Limit Retry Time-out Period and Output Under-voltage/Over-voltage Filter Delay Timer Changed PG Reset Delay and Thermal Shutdown Retry Timeout Period(16) Changed definition for Soft Start Adjustment input (ILIM) Changed drawings in Typical Applications Changed drawing in Type III Compensation Network Changed table for Soft Start Selection Removed PC34713EP/R2 from the ordering information and added MC34713EP/R2 Changed the data sheet status to Advance Information Made changes to Switching Node (SW) Pin, BOOT Pin (Referenced to SW Pin), Output Undervoltage Threshold, Output Over-voltage Threshold, High Side N-CH Power MOSFET (M3) RDS(ON)(12), Low Side N-CH Power MOSFET (M4) RDS(ON)(12), Charge Device Model Added Machine Model (MM), SW Leakage Current (Standby and Shutdown modes), Error Amplifier DC Gain(15), Error Amplifier Unit Gain Bandwidth(15), Error Amplifier Slew Rate(15), Error Amplifier Input Offset(15), High Side MOSFET Drain Voltage (PVIN) Pin Added pin 25 to Figure 3 and the 34713 Pin Definitions Added the section Layout Guidelines
3.0 4.0
2/2007 5/2007
5.0
1/2008
*
*
* *
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Analog Integrated Circuit Device Data Freescale Semiconductor
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MC34713 Rev. 5.0 12/2008

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